Gate-all-around Si nanowire FET with low thermal-budget process for monolithic three-dimensional integrated circuits

For 3D monolithic integrated (3DMI) technology, the most important task is to fabricate high performance stackable device and prevent damage on underlying device and structure during processes. In this article, we propose a green nanosecond laser crystallization and laser spike anneal process to fabricate 3D stackable ultra-thin body transistors and realize a sequentially layered integrated circuit. As identified, the possible failure mechanism of underlying device using laser process is the directly penetrated laser light and the heat from the high temperature surface. By optimizing the process conditions and stacking layer thickness, we can reduce the thickness of interlayer dielectric to about 200-nm-thin which quite reducing the delay and power loss from interconnects for 3DIC

Author(s): Tung-Ying Hsieh

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